A Model-based Hardware/Software Co-design Approach for Accelerated MPC on CPU-FPGA Hybrid Zynq Platforms

MPC/NMPC algorithms for the design of Advanced Driving Assistance Systems (ADAS) exhibit high computational complexity that is difficult to handle on standard ECU/ASIC platforms. Hybrid CPU–FPGA Zynq platforms can address this challenge by combining ARM processors with reconfigurable FPGA fabric. However, current model-based frameworks offer limited support for seamless co-design and deployment on heterogeneous hardware/software architectures. With the aim of improving the sustainability of the MPC approaches by avoiding waste of computational resources, this paper proposes a model-based workflow for the design and deployment of a hybrid hardware/software–accelerated MPC algorithm on Zynq edge platforms. Our framework allows individual functional blocks of a control application to be selectively mapped on a CPU or an FPGA accelerator to exploit their complementary strengths. We validate our workflow with a linear MPC controller for a CACC system, based on the ADMM method as the core solver. We demonstrate accurate control performance and constraint satisfaction and estimate a two-orders-of-magnitude speed-up of the ADMM solver on an FPGA compared to the ARM processor. These results demonstrate the feasibility of model-based hybrid CPU–FPGA acceleration for computationally demanding automotive control.