Exploring Time Predictability for High-Bandwidth Memory Technology

High Bandwidth Memory (HBM) is a 3D-stacked DRAM interface standard that provides higher bandwidth, lower power consumption, and a smaller footprint than DDR4 and GDDR5. It is increasingly adopted in supercomputers, datacenters, and high-end embedded platforms, such as autonomous driving systems, where it meets the performance demands of artificial intelligence and other data-intensive workloads. Beyond raw performance, many of these applications require deterministic or bounded response times, either for hard real-time safety-critical systems or to provide Quality-of-Service (QoS) guarantees in multi-tenant HPC, datacenter, and cloud environments. While performance predictability has been extensively studied for DDR memory controllers, it remains largely unexplored for HBM. Although HBM shares some characteristics with DDR, such as command reordering to reduce data bus reversals, it introduces additional challenges, including stricter timing constraints that increase command latency within bank groups. In this work, we propose an implementable architectural model of a deterministic HBM controller that addresses these challenges, together with a quantitative closed-form analysis to fully characterize its response times. We present a complete physical implementation derived from the model and describe practical simulation and synthesis toolflows enabling extensive experimental evaluation with real-world memory-intensive workloads, also including aspects such as the impact of address-to-bank/row/column mapping on HBM command performance. The proposed controller achieves a peak throughput of 13.5 GB/s per pseudo-channel and an aggregate peak throughput of 432 GB/s while providing time predictability guarantees.