A new technique is presented for designing a parallel squarer that uses both the Boothencoding and the “traditional” Folding technique. The proposed Booth-Folding technique achieves a 50% reduction of the number of partial products with respect to the simple Folded architecture, allowing a remarkable reduction of propagation delay and power dissipation. In this paper a comparison between two 32-bit squarer circuits, one using the proposed Booth-Folding technique and one using the standard Folding technique, is presented. Simulation results show that a sensible improvement in area occupation, power dissipation and propagation delay is obtained using new squarer architecture.
New Design of Squarer Circuits Using Booth Encoding and Folding Techniques / Strollo, ANTONIO GIUSEPPE MARIA; Napoli, Ettore; DE CARO, Davide. - STAMPA. - (2001), pp. 193-196. (Intervento presentato al convegno IEEE Int. Conf. on Electronics, Circuits and Systems (ICECS 2001) tenutosi a Malta nel Sept. 2001) [10.1109/ICECS.2001.957713].
New Design of Squarer Circuits Using Booth Encoding and Folding Techniques
STROLLO, ANTONIO GIUSEPPE MARIA;NAPOLI, ETTORE;DE CARO, Davide
2001
Abstract
A new technique is presented for designing a parallel squarer that uses both the Boothencoding and the “traditional” Folding technique. The proposed Booth-Folding technique achieves a 50% reduction of the number of partial products with respect to the simple Folded architecture, allowing a remarkable reduction of propagation delay and power dissipation. In this paper a comparison between two 32-bit squarer circuits, one using the proposed Booth-Folding technique and one using the standard Folding technique, is presented. Simulation results show that a sensible improvement in area occupation, power dissipation and propagation delay is obtained using new squarer architecture.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
