A modified IBIS model aimed at signal integrity analysis of system in package

Input-output buffer information specification BIS (IBIS) models are descriptions of the output buffers, used by the printed circuit board (PCB) designer to evaluate the integrity and the quality of the signals. The extension of the use of IBIS models to the system in package (SiP) world is considered. It is found that IBIS models demonstrate some limits for this application, mainly due to the poor stabilization of the supply voltage rails. An example highlighting the IBIS model limits is given. A simple hand analysis of the phenomenon is performed, from which we derive a simple solution to the problem, consisting in an improvement of the structure of the IBIS model. Simulations run making use of the improved models show a much better accuracy of the signal shapes, within 5% of the simulations run with a state-of-the-art transistor level description of the buffers.