Failure Analysis Based on Emulation Systems

To increase the throughput of electronic manufacturing companies, design, prototyping, production, installation and maintenance processes of electronic devices are generally complemented by a number of performance and parametric tests, known as Failure Analysis (FA). In this paper, major FA proposals are considered. In particular, two non- invasive solutions are presented in detail: an advanced boundary scan, using an FPGA to speed up the tests, and a logic combinational test procedure, performed by means of a fault injectable emulation system. Moreover, an innovative CPU emulation approach is proposed, particularly suited to devices that include CPU chips. In order to detect hardware faulty, the approach provides for the emulation of the same boot code designed for DUT normal operation.