Single-Flux-Quantum (SFQ) logic is a digital electronic technology known for its very low-power consumption (nW-µW) and high operating frequency (up to 100 GHz). Like any other device, SFQ-based logic circuits suffer from manufacturing process issues, specifically concerning variations in the determined values of individual components such as the critical current of a Josephson junction and inductances. This leads to the need for a deep understanding of the circuit performances, its tolerance range and, furthermore, an optimization tool to improve it achieving a certain margin for each component. In this regard, the present article delves into the techniques and the development of a new design parameter optimization algorithm, whose main goal is to increase the critical margin of the circuit. By using such a simple and efficient technique, failures due to the fabrication are avoided and performance enhancement is achieved.
Efficient Optimization of SFQ-Based Logic Circuits: Introducing a Novel Methodology for Performance and Design Enhancement / Di Marino, L.; Fienga, F.; Marrazzo, V. R.; Borghese, A.; Breglio, G.; Irace, A.; Lupo, F. V.; Mukhanov, O.; Arzeo, M.; Riccio, M.. - 1110:(2024), pp. 80-86. (Intervento presentato al convegno International Conference on Applications in Electronics Pervading Industry, Environment and Society, APPLEPIES 2023 tenutosi a ita nel 2023) [10.1007/978-3-031-48121-5_12].
Efficient Optimization of SFQ-Based Logic Circuits: Introducing a Novel Methodology for Performance and Design Enhancement
Di Marino L.;Fienga F.;Marrazzo V. R.;Borghese A.;Breglio G.;Irace A.;Riccio M.
2024
Abstract
Single-Flux-Quantum (SFQ) logic is a digital electronic technology known for its very low-power consumption (nW-µW) and high operating frequency (up to 100 GHz). Like any other device, SFQ-based logic circuits suffer from manufacturing process issues, specifically concerning variations in the determined values of individual components such as the critical current of a Josephson junction and inductances. This leads to the need for a deep understanding of the circuit performances, its tolerance range and, furthermore, an optimization tool to improve it achieving a certain margin for each component. In this regard, the present article delves into the techniques and the development of a new design parameter optimization algorithm, whose main goal is to increase the critical margin of the circuit. By using such a simple and efficient technique, failures due to the fabrication are avoided and performance enhancement is achieved.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
