Effect of gate-source bias voltage and gate-drain leakage current on the short-circuit performance of FTO-type SiC power MOSFETs

As a result of short-circuit (SC) stress tests, few commercial 1.2 kV SiC MOSFETs feature fail-to-open (FTO) behavior, that is, a permanent short-circuit between gate and source terminals, even at drain-source bias voltages as high as 600 V. Such devices are very interesting from an application point of view, since such failure mode enables implementation of hopping-home functionality at a nominal operational voltage and have thus been investigated in depth. This work delivers incremental and complementary understanding on the very timely and highly application-relevant topic of short-circuit withstand capability, aging and failure-mode of SiC power MOSFETs, pointing out new effects and dependence of the degradation state on the bias conditions during test.