The paper presents a new sense-amplifier based flip-flop. The output latch of proposed circuit can be considered as an hybrid solution between the standard NAND based SR latch and the N-C 2MOS approach. New solution provides ratioless design, reduced short circuit power dissipation and glitch free operation. Proposed flip-flop, designed for a 0.25μm technology, exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops.
A high-speed sense-amplifier based flip-flop / DE CARO, Davide; Napoli, Ettore; Petra, Nicola; Strollo, ANTONIO GIUSEPPE MARIA. - STAMPA. - 2:(2005), pp. 99-102. (Intervento presentato al convegno European conference on circuit theory and design (ECCTD) tenutosi a Cork, Ireland nel Aug. 2005) [10.1109/ECCTD.2005.1523002].
A high-speed sense-amplifier based flip-flop
DE CARO, Davide;NAPOLI, ETTORE;PETRA, NICOLA;STROLLO, ANTONIO GIUSEPPE MARIA
2005
Abstract
The paper presents a new sense-amplifier based flip-flop. The output latch of proposed circuit can be considered as an hybrid solution between the standard NAND based SR latch and the N-C 2MOS approach. New solution provides ratioless design, reduced short circuit power dissipation and glitch free operation. Proposed flip-flop, designed for a 0.25μm technology, exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
