A novel architecture for real time synthetic aperture radar signal processing is presented. Processing of SAR data requires the convolution of a sequence of echo data with a reference function. Currently quasi real time SAR signal processing is obtained by using expensive parallel computers and FFT techniques which, however, present problems if the depth of focus is small compared to the pulse length and if range dependent motion compensation is needed. The architecture presented in this paper uses time domain processing which overcomes the above mentioned problems. Real time processing is achieved by using a signum coded algorithm in which raw data and reference function are coded with a single bit. The architecture is based on a systolic array, ideally suited for implementation in custom VLSI circuits
A VLSI architecture for real time processing of one-bit coded SAR signals / Franceschetti, Giorgio; M., Tesauro; Strollo, ANTONIO GIUSEPPE MARIA; Napoli, Ettore; C., Cimino; Spirito, Paolo; Mazzeo, Antonino; Mazzocca, Nicola. - (1998), pp. 282-286. (Intervento presentato al convegno International symposium on signals systems and electronics (ISSE 98) tenutosi a Pisa, Italy nel 29 Sept.-2 Oct. 1998) [10.1109/ISSSE.1998.738082].
A VLSI architecture for real time processing of one-bit coded SAR signals
FRANCESCHETTI, GIORGIO;STROLLO, ANTONIO GIUSEPPE MARIA;NAPOLI, ETTORE;SPIRITO, PAOLO;MAZZEO, ANTONINO;MAZZOCCA, NICOLA
1998
Abstract
A novel architecture for real time synthetic aperture radar signal processing is presented. Processing of SAR data requires the convolution of a sequence of echo data with a reference function. Currently quasi real time SAR signal processing is obtained by using expensive parallel computers and FFT techniques which, however, present problems if the depth of focus is small compared to the pulse length and if range dependent motion compensation is needed. The architecture presented in this paper uses time domain processing which overcomes the above mentioned problems. Real time processing is achieved by using a signum coded algorithm in which raw data and reference function are coded with a single bit. The architecture is based on a systolic array, ideally suited for implementation in custom VLSI circuitsI documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
