A truncated binary squarer is a squarer with a n bit input that produces a n bit output. The proposed design minimizes the mean square error of the squarer and results in a very simple and fast circuital implementation. The squarer, compared against state of the art circuits, provides a reduction of the mean square error ranging from 20% to 5%. At the same time, the proposed squarer is able to reduce the power dissipation, reduce the silicon area occupation, and increase the maximum working frequency. Implementations results are provided for a 0.18um technology.
A Novel Truncated Squarer with Linear Compensation Function / Garofalo, Valeria; Coppola, Marino; DE CARO, Davide; Napoli, Ettore; Petra, Nicola; Strollo, ANTONIO GIUSEPPE MARIA. - STAMPA. - (2010), pp. 4157-4160. (Intervento presentato al convegno IEEE Int. Symp. on Circuits and Systems (ISCAS 2010) tenutosi a Parigi nel 30 Maggio - 2 Giugno) [10.1109/ISCAS.2010.5537591].
A Novel Truncated Squarer with Linear Compensation Function
GAROFALO, VALERIA;COPPOLA, MARINO;DE CARO, Davide;NAPOLI, ETTORE;PETRA, NICOLA;STROLLO, ANTONIO GIUSEPPE MARIA
2010
Abstract
A truncated binary squarer is a squarer with a n bit input that produces a n bit output. The proposed design minimizes the mean square error of the squarer and results in a very simple and fast circuital implementation. The squarer, compared against state of the art circuits, provides a reduction of the mean square error ranging from 20% to 5%. At the same time, the proposed squarer is able to reduce the power dissipation, reduce the silicon area occupation, and increase the maximum working frequency. Implementations results are provided for a 0.18um technology.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
