In this contribution we present a transmission-line based model developed to accurately describe the power and ground-line interconnections of modern digital ASICs. The proposed model employs transmission-lines as the core component to properly describe both the capacitive and inductive behavior of the metal lines. In addition, the non-linear frequency dependence of the line resistance, due to the skin-effect, is modeled with an additional lumped model. The model is completely derived from measurement data, and allows describing both in house and third parties ASICs. High frequency S-parameter measured data are used to benchmark the model. Finally, on-board voltage measurements of a Numonyx 64Mbit flash memory are performed and compared with transistor level simulations.

An experimental power-lines model for digital ASICs based on transmission-lines / Costagliola, Maurizio; DE CARO, Davide; A., Girardi; R., Izzi; Rinaldi, Niccolo'; M., Spirito; Spirito, Paolo. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - 20:1(2012), pp. 162-166. [10.1109/TVLSI.2010.2090368]

An experimental power-lines model for digital ASICs based on transmission-lines

COSTAGLIOLA, MAURIZIO;DE CARO, Davide;RINALDI, NICCOLO';SPIRITO, PAOLO
2012

Abstract

In this contribution we present a transmission-line based model developed to accurately describe the power and ground-line interconnections of modern digital ASICs. The proposed model employs transmission-lines as the core component to properly describe both the capacitive and inductive behavior of the metal lines. In addition, the non-linear frequency dependence of the line resistance, due to the skin-effect, is modeled with an additional lumped model. The model is completely derived from measurement data, and allows describing both in house and third parties ASICs. High frequency S-parameter measured data are used to benchmark the model. Finally, on-board voltage measurements of a Numonyx 64Mbit flash memory are performed and compared with transistor level simulations.
2012
An experimental power-lines model for digital ASICs based on transmission-lines / Costagliola, Maurizio; DE CARO, Davide; A., Girardi; R., Izzi; Rinaldi, Niccolo'; M., Spirito; Spirito, Paolo. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - 20:1(2012), pp. 162-166. [10.1109/TVLSI.2010.2090368]
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11588/371782
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